With the miniaturization and increasing complexity of semiconductor technologies, semiconductor devices become more easily affected by various defects or impurities. Failure of a single metal wire, diode, or transistor often constitutes defects of an entire chip. To solve this problem, conventional solutions include use of fuses or fusible links formed in the integrated circuits (ICs) to ensure usability of the ICs.
Fuses are used to connect redundant circuits in the ICs. When defects are detected in a circuit, the fuses can be used to repair or replace the defective circuit. In addition, fuses can provide a programming function. A chip may include a circuit, a device array, and a programming circuit. With data externally inputted, the circuit design may include a programming circuit. For example, in a programmable read-only memory (PROM), an open circuit is produced by blowing open a fuse, having a logic state “1”, while an unopened fuse maintains a connected state having a logic state “0”.
Conventional fuse structures include a polysilicon fuse structure. The polysilicon fuse structure is usually simultaneously formed when forming a transistor having a high-K gate dielectric layer and a metal gate layer formed by a gate last process. In the gate last process, a dummy gate structure is formed on a semiconductor substrate. The dummy gate structure includes a high-K dielectric layer, a protective layer on the high-K dielectric-layer, and a polysilicon layer on the protective layer. A metal layer is then used to replace the polysilicon layer to form the gate structure of the transistor.
During the gate last process, when the dummy gate structure is formed on the semiconductor substrate, the polysilicon fuse structure is formed on a shallow trench isolation (STI) structure. FIGS. 1-2 depict formation of a conventional semiconductor structure.
In FIG. 1, a semiconductor substrate 100 is provided including a STI structure 101 formed therein. A high-K dielectric layer 102 is formed on the semiconductor substrate 100 and on an STI structure 101. A protective layer 103 is formed on the high-K dielectric layer 102. A polysilicon layer 104 is formed on the protective layer 103.
In FIG. 2, a portion of each of the polysilicon layer 104, the protective layer 103, and the high-K dielectric layer 102 is removed from the semiconductor substrate 100 and from the shallow trench isolation structure 101 by an etching process. A dummy gate structure 110 is thus formed on the semiconductor substrate 100, and a fuse structure 120 is formed on the shallow trench isolation structure 101.
The dummy gate structure 110 includes: a high-K dielectric layer 102a, a protective layer 103a on the high-K dielectric layer 102a, and a polysilicon layer 104a on the protective layer 103a. The fuse structure 120 includes: a high-K dielectric layer 102b, a protective layer 103b on the high-K dielectric layer 102b, and a polysilicon layer 104b on the protective layer 103b. After the dummy gate structure 110 is formed, the polysilicon layer 104a of the dummy gate structure 110 is removed from the protective layer 103a. A metal gate layer is then formed on the protective layer 103a to form a gate structure of the transistor.
Problems arise, however, because the fuse structure formed on the protective layer and the high-K dielectric layer provides unstable device performance.